Decreasing a power-supply voltage effectively reduces power consumption of a semiconductor integrated circuit. This is because power consumption of a transistor included in a semiconductor can be reduced in proportion to the square of the power-supply voltage. Further, a switching operation speed (operating frequency) of the transistor is approximately proportional to the power-supply voltage. There may be a case where the logic circuit does not require a high operating frequency. In such case, decreasing the power-supply voltage and the operating frequency effectively reduces power consumption of the semiconductor integrated circuit. This is known as the Dynamic Voltage and Frequency Scaling (DVFS) controls technology.
While the DVFS control is very effective for low-power consumption, installing this technology on a chip causes various problems. The problems include a method of transmitting signals between a DVFS control region and the other power supply regions when the DVFS control is used for part of power supply regions in the chip. Generally, as mentioned above, a variation in the power-supply voltage almost linearly varies the operating frequency of the transistor. An inverse of this frequency is equivalent to the signal propagation delay time of the transistor. The signal propagation delay time of the transistor is inversely proportional to the power-supply voltage. A variation in the power-supply voltage due to the DVFS control greatly varies operating speeds of the DVFS control region and the other regions and is incapable of a synchronization design presently widely used for signal exchange.
An important promising technology for synchronization is applied to clock signals distributed to the DVFS control region and the other regions and synchronizes phases of the clock signals at the corresponding nodes. The synchronization design can eliminate the wait time (latency) for signal exchange as a disadvantage of asynchronous designs and simplifies a protocol for exchanging signals. For example, Non-patent Documents 1 and 2, Patent Documents 1, 2, and 3 describe the synchronization design under the DVFS control.    Non-patent Document 1: Toshihide Fujiyoshi, Shinichro Shiratake, Shuou Nomura, et al., “A 63-mW H.264/MPEG-4 Audio/Visual Codec LSI With Module-Wise Dynamic Voltage/Frequency Scaling”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, No. 1, January 2006, pp 54-62.    Non-patent Document 2: Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake, et al., “Low-Power Design Methodology for Module-Wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems”, 2006 IEEE 5D-1 pp 533-540.    Patent Document 1: Japanese Unexamined Patent Publication No. 2006-041129    Patent Document 2: Japanese Unexamined Patent Publication No. 2006-086455    Patent Document 3: Japanese Unexamined Patent Publication No. 2005-100269